Soldermask on via holes
There are 3 ways our customers prepare their layouts with respect to covering via-holes with soldermask:
As necessary background information we need to briefly introduce you into the technology of applying soldermask to the boards.
- First we cover the whole surface of the production panel with soldermask ink and then dry the panel (printing the soldermask)
- The ink we use is a UV sensitive material. When exposed to UV-light, the ink will harden (exposing the soldermask)
- Ink that is not exposed remains soft and can be washed away using a 1% alkalic solution (developing the soldermask)
The easiest production method is to have all vias open from both sides. The vias will be clean. They will not contain any contamination nor soldermask. The next picture shows vias free of soldermask. We did not expose the soldermask on the via pads so that it remains soft and is washed away during the developing process.
Another practical production method is where the vias are covered on both sides of the PCB. We expose the soldermask on both sides of the via-pad and via-hole so it will harden and stay on the via-pad and over the via-hole to close it. There is a risk however that (mostly in case of via-holes with a larger diameter) the via-hole is not completely covered and a small opening remains in the middle.
There is a danger that chemicals get stuck in these small openings during the processes that follow after the soldermask application. These chemical can contaminate and affect for instance the chemical Ni/Au process. A further danger exists that chemicals of the Ni/Au process remain in these openings and as they are agressive chemicals they might keep on reacting in the via hole years after the board has been produced causing possible failures in usage of the PCB in its application.
The third case (vias covered from one side and open from the other side of the PCB) is the most problematic in production. This design creates a pocket. We expose the soldermask from one side but not from the other side. This soldermask in the middle of the via-hole will only be half polymerised. During the baking process this material can come out of the hole from the open side and contaminate the copper surface and thus disturb the surface finishing process. The pictures below shows a typical failure.
Vias and Chemical Nickel-Gold (ENIG)
Vias that are not completely covered or not properly filled with soldermask may create “skip pads” in the ENIG process.
Till now we didn”t receive any reasonable explanation from our material suppliers nor did we found one elsewhere that reveals the source of this problem. However supplier advise and long term experience guide us to two possible solutions to avoid the issue:
- Modify the layout so that all vias are open. Our engineers favour this solution. Sadly this is not always accepted by our customers or the design may not allow it.
- Apply the soldermask after the ENIG process. This is a costly solution as all copper surfaces are gold-plated and the soldermask adhesion becomes worse.
For closed via-holes we have developed an alternative solution which avoids chemicals getting trapped in the partially closed via-holes during developing of the soldermask or during application of the Ni/Au. Before the coating the entire panel with soldermask we selectively print soldermask into the via holes using a stencil. During a second print run we then cover the whole panel. This way the via-holes are completely filled with soldermask. An even layer of soldermask now covers the via-holes leaving no pockets to hold residual chemicals. We have used this technique for over 6 months, and it has proved successful in dramatically reducing the number of skip pad problems.
The following movies show this process of via filling and soldermask printing.
Setting up the machine:
Printing the soldermask into the via holes:
Result after filling the via holes:
Cover the panel with soldermask:
Result after printing the soldermask:
Drying the soldermask layer: