Archive for category: PCB production
Standard and predefined build-ups
A few months ago, prepreg construction 2125 was removed from the available prepreg list of 370HR and IS400, 2 of our main FR4 material types. We exchanged this prepreg type with construction 2116. The thickness of 2116 differs from the 2125 with approximately 20 µm. At first we assumed it wouldn’t have much influence on the final thickness of the boards.
Only, some of our standard build-ups contained many sheets of this type – our standard 6-layer board contained 7 of these – which resulted in an unexpected final thickness, often too thick.
So, we had some work to do: checking out and updating all the build-ups our customers can chose from using the build-up selector.
We take the opportunity now to explain a bit more on how to read and understand the values we show in our PCB Configurator tool, referring to this subject.
The thickness label
This is the value we show in the selection box: Board thickness
This is not the final thickness of the board but a part of the name of a certain build-up. We try to keep the thickness of the actual build-up situated in a range of +/- 10 percent of the label value.
If not, probably due to selection of high Cu thickness, it will be shown.
The Total material thickness
Here we show the sum of all theoretical thicknesses of the used base material:
- Core thickness
- Prepreg thickness
- Cu layers (inner and outer)
NO plated Cu thickness is included.
The final board thickness
The calculated final board thickness is the material thickness + the plating thickness and the thickness of all additional layers, such as soldermask, legend… This calculated value should be within 10 percent from the measured value.
How to measure?
Measure on a spot without Cu, adding the thickness of the Cu from the outer-layers and the Cu plating and, if any, additional layers.
Details of the build-up construction
we show in the PCB Configurator tool can be discovered using the mouse-over function integrated in the buildup image.
You can see the core thicknesses, Cu thicknesses and the used prepregs appearing.
In Standard Pool, all our standard and predefined build-ups are constructed using these cores and prepreg types: check our download page with the list of used material types and their datasheets.
- Core: 100, 200, 360, 710 µm (with Cu foil: 12/12,18/18, 35/35 or 70/70 µm)
- Prepreg: PR1080 (70 µm), PR2116 (120 µm) and PR7628 (180 µm)
- Other available core thicknesses: 510 µm, 1000 µm and 1200µm (stock not guaranteed and only used in “special Build-up”; add the build-up construction in your dataset in this case)
In RF Pool, we have 3 additional material types available. (Be aware that not all thicknesses have guaranteed stock)
- RO4350B: 100, 168, 254, 338, 508, 762, 1524 µm (18/18)
- Bold ones are used in standard RF buildups and are also available in 35/35 and have guaranteed stock
- RO4003C: 203, 305, 406, 501, 813 and 1524 µm (18/18)
- Prepreg RO4450F: 100 µm
- I-Tera: 254, 360 and 508 µm (18/18)
- Bold ones are used in standard RF buildups and have guaranteed stock
In IMS Pool, we selected Polyterm TC-Lam 1.3.: 1500/100/35 (Aluminum alloy/dielectric/Cu thickness)
Soldermask on via holes
There are 3 ways our customers prepare their layouts with respect to covering via-holes with soldermask:
As necessary background information we need to briefly introduce you into the technology of applying soldermask to the boards.
- First we cover the whole surface of the production panel with soldermask ink and then dry the panel (printing the soldermask)
- The ink we use is a UV sensitive material. When exposed to UV-light, the ink will harden (exposing the soldermask)
- Ink that is not exposed remains soft and can be washed away using a 1% alkalic solution (developing the soldermask)
The easiest production method is to have all vias open from both sides. The vias will be clean. They will not contain any contamination nor soldermask. The next picture shows vias free of soldermask. We did not expose the soldermask on the via pads so that it remains soft and is washed away during the developing process.
Another practical production method is where the vias are covered on both sides of the PCB. We expose the soldermask on both sides of the via-pad and via-hole so it will harden and stay on the via-pad and over the via-hole to close it. There is a risk however that (mostly in case of via-holes with a larger diameter) the via-hole is not completely covered and a small opening remains in the middle.
There is a danger that chemicals get stuck in these small openings during the processes that follow after the soldermask application. These chemical can contaminate and affect for instance the chemical Ni/Au process. A further danger exists that chemicals of the Ni/Au process remain in these openings and as they are agressive chemicals they might keep on reacting in the via hole years after the board has been produced causing possible failures in usage of the PCB in its application.
The third case (vias covered from one side and open from the other side of the PCB) is the most problematic in production. This design creates a pocket. We expose the soldermask from one side but not from the other side. This soldermask in the middle of the via-hole will only be half polymerised. During the baking process this material can come out of the hole from the open side and contaminate the copper surface and thus disturb the surface finishing process. The pictures below shows a typical failure.
Vias and Chemical Nickel-Gold (ENIG)
Vias that are not completely covered or not properly filled with soldermask may create “skip pads” in the ENIG process.
Till now we didn”t receive any reasonable explanation from our material suppliers nor did we found one elsewhere that reveals the source of this problem. However supplier advise and long term experience guide us to two possible solutions to avoid the issue:
- Modify the layout so that all vias are open. Our engineers favour this solution. Sadly this is not always accepted by our customers or the design may not allow it.
- Apply the soldermask after the ENIG process. This is a costly solution as all copper surfaces are gold-plated and the soldermask adhesion becomes worse.
For closed via-holes we have developed an alternative solution which avoids chemicals getting trapped in the partially closed via-holes during developing of the soldermask or during application of the Ni/Au. Before the coating the entire panel with soldermask we selectively print soldermask into the via holes using a stencil. During a second print run we then cover the whole panel. This way the via-holes are completely filled with soldermask. An even layer of soldermask now covers the via-holes leaving no pockets to hold residual chemicals. We have used this technique for over 6 months, and it has proved successful in dramatically reducing the number of skip pad problems.
The following movies show this process of via filling and soldermask printing.
Setting up the machine:
Printing the soldermask into the via holes:
Result after filling the via holes:
Cover the panel with soldermask:
Result after printing the soldermask:
Drying the soldermask layer:
Eurocircuits”role in the project sets a new competitive standard
Making efficient pooling panels belongs to the core business of Eurocircuits. It is a necessity to ensure cost-effective production of prototypes or small batches.
Eurocircuits started as a trader of printed circuit boards in 1991. Soon after, in 1993 we got involved in production. It has been our aim from the start to use pooling techniques for a number of reasons :
- Save cost by increasing production efficiency
- Save the environment by reducing waste
The idea of making pooling panels was not new in 1993. On the Benelux market a dutch company was already successfully offering single sided boards in pooling since the eighties of the last century. For double sided boards however it was not that common yet.
When we introduced combination panels for double sided boards in our own production in Hungary there was a lot of resistance from the operators and from the production management. They saw the complexity of their job increase, and technological challenges had to be taken care of.
Now, almost 20 years later, most technology issues have been taken care of, except for one major area, the galvanic copper plating.
For this galvanic process, the design of the PCB plays a vital role in the outcome of the process. In pooling panels there is even an influence of the design of one board on the copper deposition on surrounding designs. That means that we have to be very careful how to build our panel layouts.
The restrictions in panel configuration create limitations that affect the efficiency in our production. As a producer you can look at this problem in two ways:
- Focus on efficiency and accept uneven copper distribution. Also accept that the quality of the PCB”s produced for one customer can be influenced by the design of another pcb on the same pooling panel.
- Focus on quality – stick to an even distribution and minimum copper plating thickness all over the panel. Accept that part of the panel surface gets lost because of extra copper areas and spacing introduced to balance out the galvanic layer. Also accept that not all jobs can be pooled with acceptable plating results.
Eurocircuits decided not to take any plating quality risks. We accepted the restrictions dictated by the plating process for a long time.The Elsyca Intellitool matrix copper plating is going to remove these restrictions.
Project partners :
Elsyca Intellitool plating – the concept
Elsyca Intellitool is a software controlled electroplating tooling concept developed by Elsyca. It reduces the pattern dependence of the deposited layer of copper on the boards. The main change from a standard plating cell is the introduction of a controllable grid ( matrix) of anode segments, at a small distance of the board to be plated.
The concept consists of 3 parts :
- 1.A simulation and optimisation tool which is a further development of Elsyca Smartplate, a software we use at Eurocircuits to simulate the plating process and to decide if a pooling panel is fit for production or not. The simulation tool optimizes the current on each anode segment in time to yield the desired plating thickness and uniformity on the board. The simulations counts with parameters like properties of the plating tank, design of the pcb, resisitivity of the substrate. The result of the optimization is sent to the control unit to feed the matrix.
- 2.The matrix feeder contains a microprocessor that reads the calculated pattern of the current, and controls a matrix of digital to anode converters (DACs). This imposes the correct current on each anode segment ( pin). An amplification of the current can be implemented.
- 3.The anode matrix, mounted on a printed circuit board. Each anode pin is connected to the matrix feeder.
Elsyca Intellitool is organising the anodes as a matrix with the same size as the panel to be plated, and every point in the matrix can plate with a different current. All individual currents can be controlled in time and intensity.This way the current density is not spread evenly over the panel, but is adjusted to the differences in copper distribution in the pcb design. This can be useful to balance differences in copper distribution within a single board, but gets even more interesting when there are different designs combined on one panel ( pooling-panel).
Elsyca Intellitool – in practice.
Eurocircuits is using the software from Elsyca to simulate plating (Smartplate) and judge the plating feasabilty of its pooling panels. Intellitool is going to take us a step further. We are not going to use the software just for making a judgment. The results of the simulations will be used to control the plating process by instructing each of the anodes in the matrix on the current to be used and the time to be plated.
The Elsyca Smartplate CAM output is sent directly from our UCAM Cam system to the plating line to control the process. Operator influence on the process will be eliminated.
Our plating process will be integrated in our production processes in a similar way as is now the case for CNC machines, test equipment, etc.
Elsyca Intellitool – labo test
To test the concept Elsyca made a labo plating setup. You can read an abstract of the concept and the labo test results
Elsyca Intellitool – testing in a production environment
Eurocircuits and Elsyca are testing the Elsyca Intellitool concept in a purpose built galvanic cell in our production site Eurocircuits Aachen Gmbh in Baesweiler, Germany.
The galvanic cell is built to treat one standard size Eurocircuits pooling panel ( 530 x 460 mm ) The PCB pattern on the pooling panel will vary from one production run to another.
The cell contains two anode arrays ( one for the front side, one for the backside of the pcb panel)
The tank is filled with MacDermid specialised chemicals for electroplating printed circuit boards, and the Eurocircuits pooling panel is precisely positioned between the two anode arrays.
Testing the Elsyca Intellitool production cell – November 17-2011
On November 17 tests with production panels taken out of regular production batches in Eurocircuits Aachen were plated in both our conventional plating line and in the Intellitool testcell.
Trials were conducted to evaluate the Intellitool concept as follows :
1. Test to improve the copper distribution on the panel against the conventional line :
2. Test to speed up the plating process with similar copper distribution as in the conventional line