Eurocircuits integrates EAGLE CAD software

Eurocircuits integrates EAGLE CAD software

Eurocircuits have been appointed pan-European Value-Added Reseller for CadSoft’s EAGLE PCB design software. Now you can buy EAGLE CAD software licences and upgrades directly from our website on your Eurocircuits account – no need to set up new accounts and payment procedures. How?

 

 

 

Why do we offer a CAD package?

We want to offer our customers more than just a top quality prototype and small batch PCB service. We want to help them speed up their development cycle and get their products to the market faster. The key to this is integration. We want to provide the tools for an integrated workflow from design to assembled product. Whether you are a prototype designer or a small batch manufacturer, an integrated workflow will deliver faster product development with less risk of error and lower costs.

Downstream we have integrated our PCB and stencil products with reflow soldering. This is already showing benefits. Customers report that using our bench-top stencil printer they can cut assembly time by up to 75%. In particular the eC-registration system aligns the board and stencil fully automatically, cutting out the time-consuming manual alignment needed on traditional printers. Our bench-top reflow oven completes the process.

A CAD package allows us to integrate upstream.

Why EAGLE?


Because it has proved itself over the last 20 years to be one of the most popular CAD packages around. It is easy to learn, easy to use and affordable. It has a powerful range of functions and proven support. Find out more

 

 

What is EAGLE Integration?

We have been working closely with CadSoft for the last two years or so. It is already possible to upload EAGLE BRD data files directly into our system without the need for conversion. You can already use EAGLE design rule check templates (DRU files) to help you keep board costs down. Each DRU file reflects the specifications of one of our pooling services so you can make sure that your board fits the most cost-effective one.

Now in EAGLE V6 a new “PCB quote” button takes integration one step further. It directly enters the job parameters from EAGLE into our price calculators at the click of a mouse. To get a price or place an order all you need to type in is the number of boards you need and how quickly you want them. Board size, number of layers, material thickness, copper weights etc are all entered automatically from EAGLE. If you have used an Eurocircuits DRU file you will also know that your design fits perfectly into your chosen pooling service. See how it works.

Launch Discount

To launch this new service we are offering a discount key worth €30 against a Eurocircuits PCB order if you buy an EAGLE licence from us between now and 31 May 2012.

 

See the full * terms and conditions of the offer.

 

 

 

Eurocircuits BLOG”s

EAGLE integration is not the only extra service we are offering to PCB designers. Look on our home page for a wealth of technical papers, guidelines and videos on PCB design and manufacture. Feel free to comment on this BLOG post or on any of the others. If there are other topics you’d like us to BLOG or if you’d like to share a technical post with other Eurocircuits users, please tell us at euro@eurocircuits.com

Eurocircuits data preparation – Single Image (part I) – drill data and copper image

Have you ever wondered what we are doing to your data when the order status is Single Image? Here is the answer based on the instructions we give to our data preparation engineers. Many of the steps described below are automated for speed and accuracy but we have ignored this to make a clearer presentation. More information on our requirements can be found on the home page under “Technology Guidelines”.

Stage 2 – Single Image data preparation (Single Image and Single Image Cross Check)

The name “Single Image” may be slightly confusing as it includes both single circuits and customer panels or assembly arrays. We use it to mean what we will deliver to the customer (individual circuit or panelised array) in contrast to our pooled production panels.

Build the job

  • load the job data received from Stage 1 (Analysis of PCB CAD data)
  • remove everything outside the board outline.
  • build a job netlist from the drill and Gerber data. We will use this later to check that we have not made any mistakes during the data preparation. If you have supplied an IPC netlist from your CAD system we will check the job netlist against this at this stage and raise an exception if we find discrepancies.
  • save a copy of the layers as received as a reference for later checks.
  • load the correct build-up for the job using the material thickness/copper thickness etc specified in the order
  • save the job.

Prepare the drill layer(s)

  • calculate the Nominal Hole Size. Where our standard tolerances (+/- 0.1 mm) apply, the nominal hole size is the finished hole size specified in the data (e.g. 0.80 mm). Where the designer has specified his own tolerance (e.g. +0.1/-0.00) we will aim to produce a hole in the middle of this tolerance band (so the Nominal Hole Size will be 0.85 mm).
  • increase the Nominal Hole Size to the Production Hole Size to accommodate the plating on the hole walls, the mechanical tolerances of the drilling machines etc. This is to ensure that every finished hole size is within tolerance. The rules are:
    • plated holes with finished diameter of 0.45 mm or less (taken to be via holes): increase by 0.1 mm.
    • plated holes with finished diameter of 0.50 mm or more (taken to be component holes): increase by 0.15 mm.
    • non-plated holes: increase by 0.05 mm. This is due to the bounce-back of the laminate: the drilled hole is always slightly smaller than the drill diameter.
  • Sort and regroup all drills and slots in the correct functional drill layer.
    • Put all drill and slots – PTH and NPTH – to the first drill run
    • Move any NPTH drill, slot or inner cut-out that is or can be seen as part of the board profile to the profiling run.
    • Move all NPTH drills larger then 6.00mm to the profiling run.
    • Move all NPTH drills and slots that are in a copper area (pad or plane) to the second drill run or the profiling run as per production requirements.

There are 3 possible steps in the production flow where we can drill holes:

  • First Drill Run or plated drill layer:
      • This is one of the first steps in production. All holes drilled here will become plated (PTH)
      • unless the hole is being covered with dry film, this process is commonly known as “tenting”
  • or “tented NPTH hole”. Tented NPTH holes MUST have a copper clearance of 0.30mm and can
  • have a maximum size of 6.00mm.
  • Second Drill Run or non-plated drill layer:
    • Is performed after the electroless plating process (or blackhole process). All holes here are non-plated (NPTH)
  • Profiling run or rout layer:
    • Is the last step where the profiling of the board is done. These holes are also non-plated (NPTH)

Outer Layer preparation

  • Clean the data
    • Replace any painted pads and areas with proper flash pads and polygons. Painted features filled with small draws were common in old-fashioned standard Gerber data but are not needed with Extended Gerber where you can define any pad shape or filled area you require.


Check for missing copper pads on plated-through holes (PTH).

  • Check non-plated holes (NPTH)
    • Any NPTH hole which has a copper pad that is smaller than the hole, remove the copper pad
    • For the NPTH in the first drill run (Tented NPTH): Check the drill to copper clearance, it should be minimal 0.30mm.
      • Repair if needed by creating 0.30mm clearance to copper (=same repair methods/restrictions as Minimum copper to edge clearance in DRC – see article about Data Analysis)
      • If impossible to repair then move the NPTH to the second drill run or the profiling run as per production requirements.
  • Check and repair the copper free area of 0.25mm for all elements from the rout layer (=same repair methods/restrictions as Minimum copper to edge clearance in DRC)
  • Run automated design-rule checks (DRCs) to find violations against the minimum required design specifications of the chosen service. At this stage, any violation found should normally be repairable by us.

To ensure a robust end product with optimum plating, no drill breakout and, where relevant, good solderability, we look for a minimum annular ring of copper around the hole. This ring is measured from the production hole (the TOOLSIZE) which is oversized from the finished size (the ENDSIZE) to allow for the plating in the holes. For inner layers the annular ring required is larger than for outer layers to compensate for any movement in the material during bonding. For the values required see “PCB Classification” under “Technology guidelines” on our home page.
  • Check and repair minor copper defects which may cause problems in production: peelables (see PCB Design Guidelines p. 11), pinholes and copper slivers:
    • The dimensional values of the copper defects to be detected depend upon the pattern class – Peelables and Pinholes are filled, Slivers are removed.
  • Save the job.

Inner layer preparation

  • Clean the data as for outer layers.
  • Remove all non-functional pads
  • Check for missing copper pads on connected plated-through holes
  • Check and repair the copper free area of 0.25mm for all elements from the rout layer (=same repair methods/restrictions as Minimum copper to edge clearance in DRC).
  • Check and repair all thermal pads as needed
  • Check for proper thermal to plane connections, rotate the thermal if needed – Min thermal “air-gap” should be 0.20mm.
  • Run automated design-rule checks (DRCs) to find violations against the minimum required design specifications of the chosen service. At this stage, any violation found should normally be repairable by us.
  • Save the job.

This is the end of the drill data and copper image preparation. The next article will cover Soldermask preparation, Silk screen (legend), coding on PCB”s, making customer panels, machine outputs: “drill layer, rout layer, V-cut layer”, SMD paste layers and optional other layers.

Eurocircuits data preparation – Analysis

Have you ever wondered what we are doing to your data when the order status is Analysis or Single image? Here is the answer based on the instructions we give to our data preparation engineers. Many of the steps described below are automated for speed and accuracy but we have ignored this to make a clearer presentation. More information on our requirements can be found on the home page under “Technology Guidelines”.

Stage 1 – Analysis of PCB CAD data (Analysis and Analysis Cross Check)

Analyse the data files

  • Sort the data into Gerber files, Excellon drill files and any additional files (doc, txt, pdf, …) If the data comes in CAD format (EAGLE) convert into Gerber files, drill files etc.
  • Check the additional files: is there any job information there that is not in the Gerber/Excellon files or in the order (e.g. copper weights, soldermask colours, panel setup, tolerances, layer build-up etc)?

Convert the data into the format used by our data preparation software (DPF)

  • Upload and convert the Gerber and drill data. Is there critical information in aperture-lists, tool-lists or other files?
  • Check for undefined apertures or drill-tools (hole sizes) or 0-size apertures or drills

0-size aperture in the left image, should have been aperture 0.8 as in the right image.

Build the basic job


  • Give each file its proper description. These designators are used for subsequent automatic processing. The file may be:
    • a Copper layer: outer or inner
    • a Drill file: plated (PTH), -non-plated (NPTH), buried, blind
    • an Extra file: (solder)mask, silk(screen), rout, score, outline, paste, peeloff (mask), carbon,…
  • Stack the layers correctly in the job build
  • Align all layers exactly to each other.
  • Check that all layers “read” correctly. As we always view the data through the board from the top, the top layer should read correctly and bottom layers should be mirrored.
  • Reverse any “negative” plane layers where the Gerber image shows the pads etc that will be clear (not copper) in the finished board.
  • Create the outline layer. This layer represents the actual board size and shape.
  • Delete the board outlines from the other layers (but it’s a good idea to include them in the Gerber data so that we can make sure that all the layers are correctly aligned)
  • Save job

Mixed readable and mirrored text (left) – Top right corner cut out ? (right)

Check the data against the order and the specifications of the chosen service.

  • Check the job data against the order details:
    • number of layers, board size, single board or customer panel
    • soldermask and silk options
    • specific requirements such as edge plating, gold edge-connectors, carbon, peel-off mask, viafill etc.
    • specific requirements such as special build-ups, special materials, thickness of board and copper, specific tolerances, blind/buried vias.
  • Check the copper data against the drill files: are there any missing copper pads?
  • Check the drill data against the copper data: are there any missing drill holes?
  • Check the soldermask data against the copper pads: are there any missing soldermask pads (windows)?

Check the data against the minimum values of the chosen service

  • Check for minimum finished drill size: for example, a finished hole size less than 0.25 mm is not allowed in STANDARD pool.
  • Check for slot and cut-outs less than 0.50 mm in width – not allowed in any service.
  • Check for drill-drill distance <0.15 mm – not allowed in any service.
  • Run automated design-rule checks (DRCs) to find violations against the minimum required design specifications of the chosen service.
  • Any violation that is found will be evaluated:
    • Is it repairable by us without compromising the board functionality
    • Is the number of repairs or the complexity of the repairs needed in line with a normal data preparation process. Too much or too complex repairs are most often better solved on the customer side in the CAD system.
  • Following DRC checks are performed:
    • Minimum track width. Violations against minimum track-width will not be repaired by us
    • ]
    • Minimum isolation distance. Violations against isolation between tracks or between track and pad will not be repaired by us
    • Violations against isolation between track or pad and a copper plane can be repaired by locally withdrawing the copper plane area.
    • Repair is only possible if we do not create open nets in the copper plane.
    • Minimum ring of copper round drill holes on outer layers (Outer Annular Ring – OAR). OAR violations on via holes can be repaired by reducing the via drill size (the limit is the minimum via size for the pattern class) possibly in combination with enlarging the copper pad. All holes with finished diameter of 0.45 mm or less are considered being a via hole. OAR violations on component holes are repaired by enlarging the copper pad. The repairs can only be done provided they do not violate an isolation rule which cannot be repaired.
    • Minimum ring of copper round drill holes on inner layers (Inner Annular Ring – IAR) The same repair rules apply as for OAR violations.
    • Minimum edge of drill to copper clearance on inners for drills without copper pad (IPI). Minimum IPI value is set to minimum IAR + 0.075mm for the given pattern class:
    • Violations of IPI clearance on a copper plane are repaired by withdrawing the copper plane with the needed IPI clearance value. Repair is only possible if we do not create open nets in the copper plane. Violations of IPI clearance involving tracks can be repaired by moving the specific track away from the drill provided this is possible and that it does not create any insulation rule violation which is non repairable. Violations of IPI clearance involving pads are not repairable.
    • Minimum copper to edge clearance depending whether the board outline is to be routed or scored (V-cut) .
    • Violations against the edge clearance on a copper plane are repaired by withdrawing the copper plane with the needed edge clearance value, being 0.25mm for routed board outlines and 0.45mm for scored board outlines. Repair is only possible if we do not create open nets in the copper plane. Violations on the edge clearance involving tracks can be repaired by moving the specific track inwards the board provided this is possible and that it does not create any insulation rule violation which is non repairable. Violations on the edge clearance involving pads or drill holes are not repairable.

Move to next stage or raise an exception and halt the job

• If an exception (report of documentation problems) is required make an exception document:
  • summarize all the exceptions points
    • Data missing or unclear
    • Data incorrectly formatted or corrupted in transmission, not defined apertures or 0-size apertures
    • Readability not clear, Job build not clear,outline missing or not clear
    • The provided data do not correspond with the selections made in the order
    • DRC errors that cannot be repaired by us ( see above).
  • propose solutions where possible

• If no exception is required:
  • upload the job onto the system for next stage, single image preparation.
Our data preparation process consists of 3 steps :
  • The first step is the data analysis, what this document is about. Data analysis is performed on all inquiries placed with design files and on all orders. The purpose is to detect if the documentation provided is complete and useful to quote for or accept an order.
  • The second step is the single image preparation. In this stage we are preparing the layout so that it gets fit for production . More info about this stage follows here
  • The third step is the panelizing of different jobs on a production panel – we come back in detail to this later also.

The pictures shown in the articles about data preparation are based on real pcb orders, but have been modified to show specific problems and solutions.

Bow and Twist in Printed Circuits

What is Bow and Twist?

According to the IPC-A-600 standard bow and twist (flatness of the board) is :

“Flatness of printed boards is determined by two characteristics of the product; these are known as bow and twist. The bow condition is characterized by a roughly cylindrical or spherical curvature of the board while its four corners are in the same plane. Twist is the board deformation parallel to the diagonal of the board such that one corner is not in the same plane to the other three. Circular or elliptical boards must be evaluated at the highest point of vertical displacement. Bow and twist may be influenced by the board design as different circuit configurations or layer construction of multilayer printed boards can result in different stress or stress relief conditions. Board thickness and material properties are other factors that influence the resulting board flatness.”

Why is the flatness of a printed circuit board important?

  • During the production of the board the flatness of the panels is important for handling and for positioning the panels on the machines
  • During the assembly process the flatness of the panels is important for correct solder paste deposition and component mounting
  • Flatness is an aspect of the visual quality appearance of the boards.

What are the acceptability criteria for bow and twist?

  • For all boards the bow and twist should be 1.5 % or less
  • For boards using SMD components ( the majority of the boards) the bow and twist shall be 0.75% or less.

How to measure the bow and twist?

The IPC-TM-650 test methods manual describes the method to calculate bow and twist percentages

What can the PCB designer do to avoid bow and twist?


  • Create a symmetrical copper distribution. As far as possible aim for an even copper distribution across each layer. For multilayers as far as possible arrange signal and plane layers symmetrically around the centre of the PCB. If there are areas of very low copper density and areas of high density or full copper it”s a good idea to add copper to the low density areas to balance out the copper distribution.
  • Select a symmetrical build-up of cores, pre-pregs and copper thicknesses.

What can a PCB producer do to avoid bow and twist?

  • Select base materials that are suitable for lead-free soldering. We use for instance IS400 from Isola or NP155 from Nanya
  • Use proper pressing parameters for multilayers to reduce stress in the final PCB
  • Do not mix materials from different types or vendors, and lay up the material warp and weft correctly
  • Use horizontal ovens for the curing processes
  • Cool down the panels on a horizontal surface (for instance after hot-air solder-levelling)

What can an assembly house do to avoid bow and twist?

  • Avoid heavy thermal shock during the soldering process by using a suitable soldering profile
  • Organise adequate support during the soldering process.

Your opinion?

Even if the pcb producer and assembly house take the necessary care to avoid bow and twist the deciding factor is the design of the board.
We have been brainstorming at Eurocircuits recently to see if we can develop a tool for electronics designers to predict the risk of bow and twist. This could be in the form of an index or a visual tool in the same way as our latest plating simulation tool .
As we cannot judge how useful this is for electronics developers, we ask you to comment on this post with your opinion. If there is a genuine interest in such a tool, we will (try to) develop it. You can also give your opinion on the plating simulation tool, and suggest to us how we can improve it , Or just give your opinion in our poll below