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Designing PCBs with ball-grid array (BGA) packages on them can be tricky; getting them manufactured can sometimes be even trickier! Here we’ll discuss what to consider when designing with BGAs in a way that makes them easier to manufacture and often also cheaper.
Important: all figures in this article are correct for the time of writing for up-to-date constraints consult our classification page.
We know that as our design patterns — tracks, pads, holes, etc. — get thinner, smaller, and closer together, the more expensive a board can get. On top of that, as we go through this minituarisation process, fewer manufacturers can offer us these capabilities, at all, or at an affordable price. This means that in general it is in our interest to keep patterns as ‘large’ as possible.
Our first task is to find out from our PCB manufacturer what are their manufacturing constraints, and their price break-points. There are two primary reasons for why this is a good idea. Firstly, we won’t be designing something that isn’t manufacturable (either it’ll violate design rules or be too expensive). And, we wouldn’t be spending energy making a design with ‘large’ patterns only to find out that it costs the same as manufacturing a design with ‘smaller’ patterns.
At Eurocircuits we have a simple classification system that makes figuring all this quite easy: Pattern classes 3 to 9 and Drill classes A to E, each specifies the minimum size that determines the classification of the PCB for patterns and drills, respectively. (To determine the overall classification of a board we combine the pattern and drill classes; for example, 3A, 5D, or 8E.)
The price difference between the classes isn’t linear and sometimes there’s no difference in price between them; it depends on the details of the order (usually the total surface size of the order: PCB size multiplied by the quantity). You can discover our price breaks for any board configuration using our Visualizer; generally, though, for lower quantities 6C tends to be the cheapest point and is also our default setting . (It’s also good to know that while we can manufacture class 9E boards, it’s not a pooling option so there’s a big price jump between 8E and 9E.)
Is this an accurate generalisation?
Some components are available in several packages while others only in one; sometimes we have space on the board for large packages and sometimes we don’t. It’s usually a good idea to start a design with the largest, least-fine-pitch package possible; this will often make manufacturing cheaper and easier but will also allow us to go to a smaller package if we must, something we can’t always say about going the other way round.
Even though we collectively call them all BGAs, there are many different ‘BGA’ technologies out there and within each of those there are many variants. The potential challenges we’ll have with designing-in a particular package depends on several factors: pitch, pad size, soldermask openings, pin arrangement, and the application-specific use of pins. The amount of combinations of these variables is huge such that it makes it impractical to come up with design ‘rules’ or absolute statements about what is or isn’t possible (not just at Eurocircuits, but with any manufacturer). So instead we’ll point out what are the constraints we must consider, and what we should pay attention to when placing components and routing the board.
A selection from one type of BGA technology offered by TI. There are significant variations on the placement of pins, mainly so single signal fanout is easier. Because of this amount of variations across all BGA technologies and pin arrangements there are no rules that fit them all. [Source: 1, p28]
Soldermask-defined pad (SMD) on the left and non-soldermask defined (NSMD) pad on the right.
Let’s become familiar with one more thing before proceeding. Manufacturers often specify two kinds of possible BGA pads: Non-SolderMask-Defined or SolderMask-Defined (NSMD and SMD, respectively, which incidentally is an unfortunate choice of acronyms). In brief, soldermask-defined means that the soldermask opening is smaller than the copper pad, and non-soldermask-defined means that the soldermask openings is larger than the copper pad. Each of those has application-specific advantages and disadvantages, but NSMD seems to be generally preferred by component and PCB manufacturers.
Pitch is the distance between the centres of the pads; I/OTW is the inner-layer/outer-layer track-width constraint; I/OTP is the inner/outer track-to-pad constraint; and I/OPP is the inner/outer pad-to-pad constraint.
By now we have the relevant info from the PCB manufacturer. Right? Good. Our next task is to look at the component datasheet and its related application notes. We’re looking for at least the following:
recommended footprint and pad size for either or both SMD and NSMD techniques, and if one is preferred over the other; and
recommended ‘fanout’ (how the tracks leave pins to the rest of the board).
According to that information and the number of pins, we’ll first be able to determine if tracks need to go in between the pins. Packages with 4, 6, 8, 9, 11, or other amounts of pins, in various arrangements, can be routed without needing a track going between pads. This means that even if it’s a normally ‘difficult’ 0.4mm pitch BGA, it should be straightforward to manufacture. (For example, a 0.4mm pitch BGA with a 0.225mm diameter pad will leave an edge-to-edge gap of 0.4-0.225=0.175mm; looking at the I/OPP — inner/outer layer pad-to-pad — constraints, this is possible to be manufactured from pattern class 5!)
Two examples of BGA footprint recommendations from TI. On the left a 6-pin 0.4mm pitch BGA that’s easy and cheap to manufacture and route; at Eurocircuits from Pattern class 5 which requires a minimum pad-to-pad distance of 0.175mm. On the right an example of a 11-pin 0.5mm pitch BGA with staggered pins. Also notice that in both cases TI is recommending the NSMD pad over the SMD pad. [Sources: 1, 2]
Most likely we will need to route tracks between pads. Now the trick is to figure out if the component can be used without any vias in our application. This may be possible if the manufacturer was clever about pin placement. (For example, by allowing signals to be routed through other pads; not having pads in some areas or locations; or having larger gaps between some rows or columns.) It might also be possible to creatively map pins in a way that avoids vias; this may be possible with the flexibility of FPGA pin allocation, and with some microcontrollers that have configurable pin assignments. Not needing vias is a significant advantage since it allows cheaper manufacturing of PCBs with finer-pitch components.
If we manage to only require tracks between pads, the first thing to do is to find out what’s the distance between the edges of two adjacent copper pads (from the component datasheet). In that distance we’ll need to fit one track-width (TW) and two minimum track-to-pad (TP) distances. We’ll then look at the requirements from the PCB manufacturer to see if, and at what cost, this is possible.
The I/OPP constraint determines how close we can place pads within a certain pattern classification. If we want a track to go in between those pads we need to fit two I/OTP and one I/OTW constraints from the same class.
Here’s an example. Say we have a 0.65mm pitch BGA with a recommended pad diameter of 0.26mm. The distance between the edges of the pads is therefore
0.65mm – 0.26mm = 0.39mm
Now let’s look at pattern class 7 for outer layer routing:
Outer layer Track Width (OTW) = 0.125mm
Outer layer Track-to-Pad (OTP) = 0.125mm
So the minimum distance between the edges of adjacent pads needs to be:
Min distance = OTP + OTW + OTP
Min distance = 0.125 + 0.125 + 0.125 = 0.375mm
To know if we can fit a via in between BGA pads we need to find out whether we can fit the smallest via pad within the distance between the edges of diagonal pads. Here we assume that the via is centred; sometimes it’s helpful to offset the via towards the connected pad. OPP is the outer-layer pad-to-pad constraint.
If we do indeed need vias — sometimes called escape vias — it may get a bit more complicated: we’ll usually need to fit a plated hole and pad in between four BGA pads. We‘ll need to figure out the distance between the edges of diagonal pads. Within this distance we must fit two outer layer pad-to-pad (OPP), two outer annular aings (OAR), finished drill diameter, and hole plating (0.1mm). For Class 8E we have a minimum of:
2×0.1 + 2×0.1 + 0.1 + 0.1 = 0.6mm
For Class 7E we have:
2×0.125 + 2×0.125 + 0.1 + 0.1 = 0.7mm
Or, if we have the minimum pad diameter for the pattern class:
2xI/OPP + min pad diameter
Do those fit in the diagonal distance we got from the datasheet? (Note that sometimes there are different manufacturing constraints for ‘outer’ and ‘inner’ layers, like in our pattern class 8, so pay attention to that if it’s relevant to your layout).
Since even moving a track or a via by 0.01mm can mean being bumped into a more expensive price point it pays to be precise when routing and placing components. Grids and snapping are crucial for getting this right. Create one or more grids that fit exactly to the centre points between pads so that you could route a track in the exact middle. Also verify that your track width is actually what you expect it to be. Use these grids to place vias exactly between four pads. Offsetting vias towards the connected pad can sometimes give a little bit of extra space; if you’re using that technique, create another grid for that offset. If your tool allows it, define constraints zones for where you have BGAs. Basically, putting the effort in this setup up-front will save you a lot of time later on.
A cross-section of a filled via. Filled-via-in-pad can be a routing solution for some BGAs.
Sometimes filled-via-in-pad helps route around tight spots. This, however, has the disadvantage that the pad size needs to be at least as large as the via pad. For class 8E this is 0.4mm diameter which can be larger than the BGA pad diameter recommended by the component manufacturer. In considering filled-vias, balance the price for the extra via-filling step against the move to a higher classification; the difference in prices could be significant. (More on filled vias here.)
While we don’t recommend it, you could reduce the size of the pads specified in the datasheet to give you a bit of extra room to fit tracks and vias. This might work if you’re doing a few boards, but is quite risky otherwise. If you’re going to use a service that will assemble your boards you’ll definitely need to consult them. At Eurocircuits we’ll manufacture the board as long as it passes our usual checks except when we’re going to assemble the PCB for you. In that case our footprint verification process will reject a design with reduced pads and you’ll have to get in touch in order to see if it can be cleared for production.
By now you may be wondering how do people design with 0.4mm pitch BGA components that have hundreds and thousands of pins when everything is so tight? The solution, usually for 0.5mm pitch and finer components, is the High density Interconnects (HDI) process that allows greater density and that uses microvias that are created with laser rather than through mechanical drilling. These technologies are outside the scope of this article and are also not available from Eurocircuits.
BGAs can make our boards expensive or hard to manufacture, but with knowledge and some clever maneuvers, we can do something about it. Here are my suggestions:
Use as large features as you can given the constraints of your PCB manufacturer;
find out the price-feature-size break-points of your manufacturer in order to set your constraints;
find out all that’s available about signal fanout strategies for your component;
start with the largest package possible; and
use several grids to make sure everything is placed accurately.
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