To verify a PCB design before manufacturing, run a combination of design rule checks (DRC), manufacturer-specific DFM analysis, data verification, and impedance or stack-up review. These checks identify manufacturing problems while changes are still straightforward to make digitally, reducing the risk of avoidable prototype iterations and costly rework.
The exact checks required depend on your PCB technology, complexity, and the manufacturing process you intend to use. A design intended for HDI or controlled-impedance production requires more thorough pre-production review than a straightforward two-layer board. The sections below address the most common verification questions engineers face before placing an order.
What checks should be run on a PCB design before ordering?
Before ordering a PCB, you should run design rule checks within your EDA tool, submit your data for manufacturer-specific DFM analysis, verify your layer stack-up and impedance requirements, and review your manufacturing data for completeness. Together, these checks confirm that your design is both electrically sound and manufacturable using your chosen process.
Each check addresses a different category of potential problem. EDA-based DRC catches violations against your own design rules, such as minimum track spacing and drill sizes. Manufacturer DFM analysis evaluates your design against the specific capabilities and constraints of the intended production process. Data verification confirms that your Gerber files, drill data, and fabrication notes are complete, consistent, and unambiguous.
For PCB assembly, additional checks apply. Your bill of materials (BOM) must be complete, with accurate manufacturer part numbers, correct package references, and consistent polarity information. Placement data must align with the BOM and reflect the actual component footprints on the board. Incomplete or inconsistent assembly data is one of the most common causes of preparation delays and engineering clarifications before production can begin.
Running all of these checks before ordering is the foundation of a PCB design for manufacturability approach. Identifying problems at the data stage is significantly faster and less expensive than discovering them after boards have been manufactured.
What is a DFM check and what does it catch?
A Design for Manufacturability (DFM) check evaluates a PCB design against the manufacturing capabilities and constraints of the intended production process. It identifies features that cannot be reliably manufactured, or that fall outside the tolerances of the chosen technology, before physical production begins.
DFM analysis typically examines a range of geometric and structural parameters. Common issues caught by DFM include:
- Insufficient track clearances between conductors, which can cause short circuits during etching
- Conductor widths that are too narrow for reliable etching or current-carrying requirements
- Annular ring dimensions that are too small to guarantee reliable drill registration
- Copper-to-board-edge distances that risk copper exposure after routing
- Drill sizes and aspect ratios that exceed the capability of the intended drilling process
- Solder mask features that are too small or too closely spaced for reliable application
- Stack-up conflicts between the intended layer build-up and the available manufacturing options
It is important to understand what DFM does not cover. A DFM check evaluates manufacturability, not electronic functionality. A design can pass DFM analysis and still require engineering iterations to validate that the circuit performs as intended. DFM reduces avoidable manufacturing problems; it does not replace functional testing and engineering development.
The specific constraints caught by a DFM check also depend on the manufacturing process and technology class. Standard pooled production has different capability limits than dedicated HDI or controlled-impedance manufacturing. Always verify DFM results against the capabilities of your actual intended process.
How does a PCB visualiser help catch design errors?
A PCB visualiser helps catch design errors by creating a digital representation of how your manufacturing data will be interpreted in production. Rather than relying on your EDA tool’s own view of the design, a visualiser shows how the manufacturer’s systems read and process your files, revealing discrepancies that would otherwise only appear after boards are manufactured.
This distinction matters because the file you export from your EDA tool and the file the manufacturer interprets are not always identical. Layer assignments can be misread, aperture definitions can be ambiguous, drill files can be misaligned, and fabrication notes can conflict with the actual data. A PCB visualiser surfaces these interpretation issues before production begins.
Beyond data interpretation, a capable visualiser applies automated DFM rules to the uploaded data. This allows engineers to review flagged issues interactively, understand what each issue means for manufacturability, and decide whether to correct the design or accept a specific condition. The best visualiser tools also propose corrective actions, reducing the time needed to resolve common problems.
For assembly, a PCBA visualiser extends this verification to component placement. It checks whether placement data is consistent with the BOM, whether component packages match the footprints on the board, and whether assembly requirements are clearly defined. Catching these inconsistencies digitally avoids the engineering clarifications and delays that would otherwise slow down assembly preparation.
What’s the difference between DRC and a manufacturer’s data verification?
A design rule check (DRC) is performed within your EDA tool and validates your design against the rules you have defined in your design environment. A manufacturer’s data verification checks your exported manufacturing files against the manufacturer’s own process capabilities, interpretation standards, and production requirements. The two checks are complementary but address fundamentally different questions.
DRC answers: “Does this design comply with the rules I have set?” Manufacturer data verification answers: “Can this design be manufactured reliably using the intended process, and is the data complete and unambiguous?”
A design can pass DRC and still contain problems that only appear during manufacturer verification. Common examples include:
- Layer assignments that your EDA tool understands correctly but that are ambiguous in the exported Gerber package
- Design rules set in your tool that are less restrictive than the manufacturer’s actual process capabilities
- Missing fabrication data, such as undefined board thickness, surface finish, or copper weight
- Drill files that do not align correctly with the copper layers when imported by the manufacturer’s CAM system
- Conflicting information between the fabrication drawing and the Gerber data
Running only an in-tool DRC before ordering gives you confidence that your design is internally consistent, but it does not confirm that your manufacturing data is production-ready. Manufacturer data verification closes that gap by checking the actual files that will be used to produce your boards.
When should impedance and stack-up be verified?
Impedance and stack-up should be verified as early as possible in the design process, ideally before routing begins. Confirming the layer build-up, dielectric materials, and copper weights at the start of layout ensures that controlled-impedance track widths are calculated correctly for the actual manufacturing process, not for assumed or default values.
Leaving stack-up verification until after routing is complete creates significant risk. If the confirmed build-up differs from the assumed one, track widths calculated for impedance control may be incorrect, requiring layout changes that affect the entire board. In complex designs, this can mean substantial rework.
For designs that require controlled impedance, the verification process should include:
- Confirming the available pre-defined build-ups for your chosen PCB technology and layer count with your manufacturer
- Calculating impedance values for your critical signals using the confirmed dielectric thicknesses, copper weights, and track geometry
- Defining impedance requirements clearly in your fabrication data, specifying which layers carry controlled-impedance signals and the target impedance values
- Verifying consistency between your impedance specifications, the confirmed stack-up, and the actual track widths in your layout before submitting for production
Standard designs without impedance-controlled signals still benefit from early stack-up confirmation. Copper weight, board thickness, and layer count all affect manufacturing cost and lead time. Confirming these parameters before design completion avoids surprises when pricing and ordering.
How can design verification reduce PCB prototype iterations?
Design verification reduces PCB prototype iterations by identifying avoidable manufacturing and assembly problems before physical production begins. When issues are caught and resolved at the data stage, they do not become manufacturing defects that require another prototype build to correct. This distinction, between productive engineering iterations and avoidable manufacturing iterations, is central to an efficient prototyping process.
Productive engineering iterations are a normal and necessary part of electronics development. Testing a prototype, learning how the circuit performs, and refining the design are expected activities. These iterations cannot be eliminated and should not be. What verification addresses is a different category of problem: manufacturing issues that arise not because the design needed refinement, but because the data was incomplete, inconsistent, or outside the process capability of the intended manufacturing method.
Avoidable iterations that verification can prevent include:
- Boards returned or delayed because manufacturing data is incomplete or ambiguous
- Prototypes that fail because a DFM violation was not identified before production
- Assembly errors caused by BOM inconsistencies or incorrect component references
- Impedance performance problems caused by stack-up assumptions that differed from the actual build-up
- Rework and re-ordering costs from design features that fell outside manufacturing tolerances
Each avoidable iteration adds engineering time, manufacturing cost, logistics, and delay to the development timeline. In a structured NPI process, where the goal is to move efficiently from a validated prototype to repeatable production, these delays can have a significant impact on time-to-market. Thorough pre-production verification is one of the most effective ways to keep the development cycle on track.
How Eurocircuits helps with PCB design verification
Eurocircuits offers a free online PCB and PCBA Visualizer that applies pre-production verification directly to your uploaded manufacturing data, before you place an order. It is designed to give engineers a clear view of how their design will be interpreted for production, and to identify issues while changes are still straightforward to make.
- Over 700 DRC and DFM rules are applied automatically to check that your data is manufacturable for the selected pooling service
- An integrated build-up editor with more than 970 pre-defined builds helps confirm stack-up compatibility early in the process
- Interactive issue reporting shows exactly what has been flagged and, where possible, proposes automatic repair solutions for review and approval
- PCBA verification checks BOM completeness, component references, and placement data consistency before assembly preparation begins
- A verified component database of 450,000 parts supports component engineering and helps identify component-data problems before production
The Visualizer is available 24/7, in six languages, and is integrated directly into the Eurocircuits ordering platform. Visit the Eurocircuits services page to find further guidance on uploading your design data and running pre-production verification before your next order.