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Swissloop is a student team at ETH Zurich developing a proof of concept “Hyperloop Pod”. It’s all about high-speed travel for us, with the long-term theoretical goal of being able to reach high velocities of up to 1,000 km/h. The idea was sketched out by Elon Musk in 2013 and a yearly student competition was kicked-off by SpaceX in 2015, it last took place in 2019. Starting last year Swissloop and a few other student teams took the initiative and started the European Hyperloop Week, a competition focused on technology innovation, where we are competing now.
This year, our focus lies on a novel linear motor, intended to be more scalable and efficient. The exact details will be revealed at a later date. Developing a new motor involves various specific design requirements for the electronics of the whole system, in particular the power electronics. In order to move the pod, the current in the motor coils has to be precisely controlled. Because of this, we have opted to go for a custom design for most PCBs, amounting to almost 10 unique and custom boards. They allow us to realize three main aspects:
Being able to control the motor by combining various sensor inputs.
Being able to precisely control the current in the motor with an inverter to reproduce a target current as close as possible.
Being able to safely operate a powerful battery with a high voltage capability to drive the motor.
With the support of Eurocircuits, we were able to have an immense amount of design freedom in our latest motor. We are very thankful for this and are looking forward to bringing the whole system together!
Here are some sneak peeks of some of the Swissloop PCBs. Enjoy 🙂
We have simplified and redesigned our motor (inverter) control unit to one microcontroller and FPGA pair instead of three. This also hopefully saves us having to synchronize the different chips, where we had issues last year. The new design allowed us to maneuver around the chip shortage, as we were able to use some older microcontrollers, which we still had in stock.
As the FPGA (see below) is in a small BGA package, we resorted to using a 6-layer class 8E PCB to ensure all tolerances were met and we were able to fan out and escape most pins. Despite being on the limit of most tolerances, the end-product was surprisingly exact. This small board is stacked onto a larger 4-layer board which has almost 20 signal connectors going to the inverters and sensors. From this perspective, it is quite a centralized design. Let’s hope it works!
For this board the PCB Visualizer® was really helpful in being able to determine if the design was really manufacturable. For the interested: 256-pin caBGA, 0.8mm pitch, 0.1mm hole size.
The microscope shows great tolerances on the 0.1mm filled vias for the class 8E PCB with 0402 capacitors tightly packed in between the gaps.